From 63646e8906e062d1c1de3925cba70c4e3426a855 Mon Sep 17 00:00:00 2001 From: QMK Bot Date: Sat, 12 Feb 2022 10:29:31 -0800 Subject: Format code according to conventions (#16322) --- tmk_core/protocol/arm_atsam/adc.c | 26 +- tmk_core/protocol/arm_atsam/adc.h | 2 +- tmk_core/protocol/arm_atsam/arm_atsam_protocol.h | 4 +- tmk_core/protocol/arm_atsam/clks.c | 42 +-- tmk_core/protocol/arm_atsam/clks.h | 24 +- tmk_core/protocol/arm_atsam/d51_util.c | 34 +- tmk_core/protocol/arm_atsam/d51_util.h | 4 +- tmk_core/protocol/arm_atsam/i2c_master.c | 132 ++++---- tmk_core/protocol/arm_atsam/i2c_master.h | 4 +- tmk_core/protocol/arm_atsam/issi3733_driver.h | 200 ++++++------ tmk_core/protocol/arm_atsam/main_arm_atsam.c | 113 +++---- tmk_core/protocol/arm_atsam/main_arm_atsam.h | 2 +- tmk_core/protocol/arm_atsam/md_rgb_matrix.c | 82 ++--- tmk_core/protocol/arm_atsam/md_rgb_matrix.h | 142 ++++---- .../protocol/arm_atsam/md_rgb_matrix_programs.c | 4 +- tmk_core/protocol/arm_atsam/shift_register.c | 12 +- tmk_core/protocol/arm_atsam/spi_master.c | 22 +- tmk_core/protocol/arm_atsam/usb/compiler.h | 124 +++---- tmk_core/protocol/arm_atsam/usb/conf_usb.h | 4 +- tmk_core/protocol/arm_atsam/usb/main_usb.c | 48 ++- tmk_core/protocol/arm_atsam/usb/status_codes.h | 28 +- tmk_core/protocol/arm_atsam/usb/udc.c | 66 ++-- tmk_core/protocol/arm_atsam/usb/udc.h | 18 +- tmk_core/protocol/arm_atsam/usb/udc_desc.h | 2 +- tmk_core/protocol/arm_atsam/usb/udd.h | 2 +- tmk_core/protocol/arm_atsam/usb/udi.h | 2 +- tmk_core/protocol/arm_atsam/usb/udi_cdc.c | 158 ++++++--- tmk_core/protocol/arm_atsam/usb/udi_cdc.h | 6 +- tmk_core/protocol/arm_atsam/usb/udi_cdc_conf.h | 8 +- tmk_core/protocol/arm_atsam/usb/udi_device_conf.h | 20 +- .../protocol/arm_atsam/usb/udi_device_epsize.h | 2 +- tmk_core/protocol/arm_atsam/usb/udi_hid.c | 2 +- tmk_core/protocol/arm_atsam/usb/udi_hid.h | 2 +- tmk_core/protocol/arm_atsam/usb/udi_hid_kbd.c | 146 +++++---- tmk_core/protocol/arm_atsam/usb/udi_hid_kbd.h | 12 +- tmk_core/protocol/arm_atsam/usb/udi_hid_kbd_conf.h | 2 +- tmk_core/protocol/arm_atsam/usb/udi_hid_kbd_desc.c | 6 +- tmk_core/protocol/arm_atsam/usb/ui.c | 2 +- tmk_core/protocol/arm_atsam/usb/ui.h | 2 +- tmk_core/protocol/arm_atsam/usb/usb.c | 28 +- tmk_core/protocol/arm_atsam/usb/usb.h | 32 +- tmk_core/protocol/arm_atsam/usb/usb_atmel.h | 4 +- tmk_core/protocol/arm_atsam/usb/usb_device_udd.c | 38 ++- tmk_core/protocol/arm_atsam/usb/usb_hub.c | 76 ++--- tmk_core/protocol/arm_atsam/usb/usb_hub.h | 2 +- tmk_core/protocol/arm_atsam/usb/usb_main.h | 12 +- tmk_core/protocol/arm_atsam/usb/usb_protocol.h | 76 ++--- tmk_core/protocol/arm_atsam/usb/usb_protocol_cdc.h | 80 ++--- tmk_core/protocol/arm_atsam/usb/usb_protocol_hid.h | 102 +++--- tmk_core/protocol/arm_atsam/usb/usb_util.c | 22 +- tmk_core/protocol/arm_atsam/usb/usb_util.h | 2 +- tmk_core/protocol/chibios/chibios.c | 8 +- tmk_core/protocol/chibios/usb_driver.c | 32 +- tmk_core/protocol/chibios/usb_main.c | 24 +- tmk_core/protocol/chibios/usb_util.c | 8 +- tmk_core/protocol/host.c | 28 +- tmk_core/protocol/lufa/lufa.c | 53 ++- tmk_core/protocol/lufa/usb_util.c | 8 +- tmk_core/protocol/midi/bytequeue/bytequeue.c | 4 +- .../protocol/midi/bytequeue/interrupt_setting.c | 8 +- tmk_core/protocol/midi/midi.c | 130 ++++++-- tmk_core/protocol/midi/midi.h | 6 +- tmk_core/protocol/midi/midi_device.c | 11 +- tmk_core/protocol/midi/qmk_midi.c | 2 +- tmk_core/protocol/midi/sysex_tools.c | 2 +- tmk_core/protocol/usb_descriptor.h | 2 +- tmk_core/protocol/usb_device_state.c | 4 +- tmk_core/protocol/usb_device_state.h | 8 +- tmk_core/protocol/usb_util.c | 4 +- tmk_core/protocol/vusb/protocol.c | 4 +- tmk_core/protocol/vusb/usb_util.c | 4 +- tmk_core/protocol/vusb/vusb.c | 358 +++++++++++---------- 72 files changed, 1507 insertions(+), 1186 deletions(-) (limited to 'tmk_core/protocol') diff --git a/tmk_core/protocol/arm_atsam/adc.c b/tmk_core/protocol/arm_atsam/adc.c index 1ef1b11d57..3afcbddf10 100644 --- a/tmk_core/protocol/arm_atsam/adc.c +++ b/tmk_core/protocol/arm_atsam/adc.c @@ -27,10 +27,10 @@ uint16_t v_con_2_boot; void ADC0_clock_init(void) { DBGC(DC_ADC0_CLOCK_INIT_BEGIN); - MCLK->APBDMASK.bit.ADC0_ = 1; // ADC0 Clock Enable + MCLK->APBDMASK.bit.ADC0_ = 1; // ADC0 Clock Enable - GCLK->PCHCTRL[ADC0_GCLK_ID].bit.GEN = GEN_OSC0; // Select generator clock - GCLK->PCHCTRL[ADC0_GCLK_ID].bit.CHEN = 1; // Enable peripheral clock + GCLK->PCHCTRL[ADC0_GCLK_ID].bit.GEN = GEN_OSC0; // Select generator clock + GCLK->PCHCTRL[ADC0_GCLK_ID].bit.CHEN = 1; // Enable peripheral clock DBGC(DC_ADC0_CLOCK_INIT_COMPLETE); } @@ -39,15 +39,15 @@ void ADC0_init(void) { DBGC(DC_ADC0_INIT_BEGIN); // MCU - PORT->Group[1].DIRCLR.reg = 1 << 0; // PB00 as input 5V - PORT->Group[1].DIRCLR.reg = 1 << 1; // PB01 as input CON2 - PORT->Group[1].DIRCLR.reg = 1 << 2; // PB02 as input CON1 - PORT->Group[1].PMUX[0].bit.PMUXE = 1; // PB00 mux select B ADC 5V - PORT->Group[1].PMUX[0].bit.PMUXO = 1; // PB01 mux select B ADC CON2 - PORT->Group[1].PMUX[1].bit.PMUXE = 1; // PB02 mux select B ADC CON1 - PORT->Group[1].PINCFG[0].bit.PMUXEN = 1; // PB01 mux ADC Enable 5V - PORT->Group[1].PINCFG[1].bit.PMUXEN = 1; // PB01 mux ADC Enable CON2 - PORT->Group[1].PINCFG[2].bit.PMUXEN = 1; // PB02 mux ADC Enable CON1 + PORT->Group[1].DIRCLR.reg = 1 << 0; // PB00 as input 5V + PORT->Group[1].DIRCLR.reg = 1 << 1; // PB01 as input CON2 + PORT->Group[1].DIRCLR.reg = 1 << 2; // PB02 as input CON1 + PORT->Group[1].PMUX[0].bit.PMUXE = 1; // PB00 mux select B ADC 5V + PORT->Group[1].PMUX[0].bit.PMUXO = 1; // PB01 mux select B ADC CON2 + PORT->Group[1].PMUX[1].bit.PMUXE = 1; // PB02 mux select B ADC CON1 + PORT->Group[1].PINCFG[0].bit.PMUXEN = 1; // PB01 mux ADC Enable 5V + PORT->Group[1].PINCFG[1].bit.PMUXEN = 1; // PB01 mux ADC Enable CON2 + PORT->Group[1].PINCFG[2].bit.PMUXEN = 1; // PB02 mux ADC Enable CON1 // ADC ADC0->CTRLA.bit.SWRST = 1; @@ -81,7 +81,7 @@ void ADC0_init(void) { } // Settling - ADC0->SAMPCTRL.bit.SAMPLEN = 45; // Sampling Time Length: 1-63, 1 ADC CLK per + ADC0->SAMPCTRL.bit.SAMPLEN = 45; // Sampling Time Length: 1-63, 1 ADC CLK per while (ADC0->SYNCBUSY.bit.SAMPCTRL) { DBGC(DC_ADC0_SAMPCTRL_SYNCING_1); } diff --git a/tmk_core/protocol/arm_atsam/adc.h b/tmk_core/protocol/arm_atsam/adc.h index 9ab653e5a2..74fbb0e66f 100644 --- a/tmk_core/protocol/arm_atsam/adc.h +++ b/tmk_core/protocol/arm_atsam/adc.h @@ -34,4 +34,4 @@ extern uint16_t v_con_2_boot; void ADC0_clock_init(void); void ADC0_init(void); -#endif //_ADC_H_ +#endif //_ADC_H_ diff --git a/tmk_core/protocol/arm_atsam/arm_atsam_protocol.h b/tmk_core/protocol/arm_atsam/arm_atsam_protocol.h index 319ff8487d..db9827f6a2 100644 --- a/tmk_core/protocol/arm_atsam/arm_atsam_protocol.h +++ b/tmk_core/protocol/arm_atsam/arm_atsam_protocol.h @@ -42,6 +42,6 @@ along with this program. If not, see . # include "./usb/udc.h" # include "./usb/udi_cdc.h" -#endif // MD_BOOTLOADER +#endif // MD_BOOTLOADER -#endif //_ARM_ATSAM_PROTOCOL_H_ +#endif //_ARM_ATSAM_PROTOCOL_H_ diff --git a/tmk_core/protocol/arm_atsam/clks.c b/tmk_core/protocol/arm_atsam/clks.c index 84ed6d83af..9b9475c616 100644 --- a/tmk_core/protocol/arm_atsam/clks.c +++ b/tmk_core/protocol/arm_atsam/clks.c @@ -22,7 +22,7 @@ along with this program. If not, see . volatile clk_t system_clks; volatile uint64_t ms_clk; uint32_t usec_delay_mult; -#define USEC_DELAY_LOOP_CYCLES 3 // Sum of instruction cycles in us delay loop +#define USEC_DELAY_LOOP_CYCLES 3 // Sum of instruction cycles in us delay loop const uint32_t sercom_apbbase[] = {(uint32_t)SERCOM0, (uint32_t)SERCOM1, (uint32_t)SERCOM2, (uint32_t)SERCOM3, (uint32_t)SERCOM4, (uint32_t)SERCOM5}; const uint8_t sercom_pchan[] = {7, 8, 23, 24, 34, 35}; @@ -59,9 +59,9 @@ void CLK_oscctrl_init(void) { while (posctrl->Dpll[USE_DPLL_IND].DPLLSYNCBUSY.bit.ENABLE) { DBGC(DC_CLK_OSC_INIT_DPLL_SYNC_DISABLE); } - posctrl->Dpll[USE_DPLL_IND].DPLLCTRLB.bit.REFCLK = 2; // select XOSC0 (16MHz) - posctrl->Dpll[USE_DPLL_IND].DPLLCTRLB.bit.DIV = 7; // 16 MHz / (2 * (7 + 1)) = 1 MHz - posctrl->Dpll[USE_DPLL_IND].DPLLRATIO.bit.LDR = PLL_RATIO; // 1 MHz * (PLL_RATIO(47) + 1) = 48MHz + posctrl->Dpll[USE_DPLL_IND].DPLLCTRLB.bit.REFCLK = 2; // select XOSC0 (16MHz) + posctrl->Dpll[USE_DPLL_IND].DPLLCTRLB.bit.DIV = 7; // 16 MHz / (2 * (7 + 1)) = 1 MHz + posctrl->Dpll[USE_DPLL_IND].DPLLRATIO.bit.LDR = PLL_RATIO; // 1 MHz * (PLL_RATIO(47) + 1) = 48MHz while (posctrl->Dpll[USE_DPLL_IND].DPLLSYNCBUSY.bit.DPLLRATIO) { DBGC(DC_CLK_OSC_INIT_DPLL_SYNC_RATIO); } @@ -87,7 +87,7 @@ void CLK_oscctrl_init(void) { system_clks.freq_gclk[0] = system_clks.freq_dpll[0]; usec_delay_mult = system_clks.freq_gclk[0] / (USEC_DELAY_LOOP_CYCLES * 1000000); - if (usec_delay_mult < 1) usec_delay_mult = 1; // Never allow a multiplier of zero + if (usec_delay_mult < 1) usec_delay_mult = 1; // Never allow a multiplier of zero DBGC(DC_CLK_OSC_INIT_COMPLETE); } @@ -240,7 +240,7 @@ uint32_t CLK_enable_timebase(void) { // ptc4->COUNT16.DBGCTRL.bit.DBGRUN = 1; // wave mode - ptc4->COUNT16.WAVE.bit.WAVEGEN = 1; // MFRQ match frequency mode, toggle each CC match + ptc4->COUNT16.WAVE.bit.WAVEGEN = 1; // MFRQ match frequency mode, toggle each CC match // generate event for next stage ptc4->COUNT16.EVCTRL.bit.MCEO0 = 1; @@ -272,9 +272,9 @@ uint32_t CLK_enable_timebase(void) { DBGC(DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_SWRST_2); } // CTRLA as default - ptc0->COUNT32.CTRLA.bit.MODE = 2; // 32 bit mode - ptc0->COUNT32.EVCTRL.bit.TCEI = 1; // enable incoming events - ptc0->COUNT32.EVCTRL.bit.EVACT = 2; // count events + ptc0->COUNT32.CTRLA.bit.MODE = 2; // 32 bit mode + ptc0->COUNT32.EVCTRL.bit.TCEI = 1; // enable incoming events + ptc0->COUNT32.EVCTRL.bit.EVACT = 2; // count events DBGC(DC_CLK_ENABLE_TIMEBASE_TC0_COMPLETE); @@ -284,10 +284,10 @@ uint32_t CLK_enable_timebase(void) { pmclk->APBBMASK.bit.EVSYS_ = 1; pgclk->PCHCTRL[EVSYS_GCLK_ID_0].bit.GEN = GEN_TC45; pgclk->PCHCTRL[EVSYS_GCLK_ID_0].bit.CHEN = 1; - pevsys->USER[44].reg = EVSYS_ID_USER_PORT_EV_0; // TC0 will get event channel 0 - pevsys->Channel[0].CHANNEL.bit.EDGSEL = EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val; // Rising edge - pevsys->Channel[0].CHANNEL.bit.PATH = EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val; // Synchronous - pevsys->Channel[0].CHANNEL.bit.EVGEN = EVSYS_ID_GEN_TC4_MCX_0; // TC4 MC0 + pevsys->USER[44].reg = EVSYS_ID_USER_PORT_EV_0; // TC0 will get event channel 0 + pevsys->Channel[0].CHANNEL.bit.EDGSEL = EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val; // Rising edge + pevsys->Channel[0].CHANNEL.bit.PATH = EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val; // Synchronous + pevsys->Channel[0].CHANNEL.bit.EVGEN = EVSYS_ID_GEN_TC4_MCX_0; // TC4 MC0 DBGC(DC_CLK_ENABLE_TIMEBASE_EVSYS_COMPLETE); @@ -301,15 +301,15 @@ uint32_t CLK_enable_timebase(void) { } void CLK_delay_us(uint32_t usec) { - asm("CBZ R0, return\n\t" // If usec == 0, branch to return label + asm("CBZ R0, return\n\t" // If usec == 0, branch to return label ); - asm("MULS R0, %0\n\t" // Multiply R0(usec) by usec_delay_mult and store in R0 - ".balign 16\n\t" // Ensure loop is aligned for fastest performance - "loop: SUBS R0, #1\n\t" // Subtract 1 from R0 and update flags (1 cycle) - "BNE loop\n\t" // Branch if non-zero to loop label (2 cycles) NOTE: USEC_DELAY_LOOP_CYCLES is the sum of loop cycles - "return:\n\t" // Return label - : // No output registers - : "r"(usec_delay_mult) // For %0 + asm("MULS R0, %0\n\t" // Multiply R0(usec) by usec_delay_mult and store in R0 + ".balign 16\n\t" // Ensure loop is aligned for fastest performance + "loop: SUBS R0, #1\n\t" // Subtract 1 from R0 and update flags (1 cycle) + "BNE loop\n\t" // Branch if non-zero to loop label (2 cycles) NOTE: USEC_DELAY_LOOP_CYCLES is the sum of loop cycles + "return:\n\t" // Return label + : // No output registers + : "r"(usec_delay_mult) // For %0 ); // Note: BX LR generated } diff --git a/tmk_core/protocol/arm_atsam/clks.h b/tmk_core/protocol/arm_atsam/clks.h index 72df3a8e3f..6ee71aff8f 100644 --- a/tmk_core/protocol/arm_atsam/clks.h +++ b/tmk_core/protocol/arm_atsam/clks.h @@ -24,14 +24,14 @@ along with this program. If not, see . # include "config_led.h" # include "config.h" -#endif // MD_BOOTLOADER +#endif // MD_BOOTLOADER -#define PLL_RATIO 47 // mcu frequency ((X+1)MHz) -#define FREQ_DFLL_DEFAULT 48000000 // DFLL frequency / usb clock -#define FREQ_SPI_DEFAULT 1000000 // spi to 595 shift regs -#define FREQ_I2C0_DEFAULT 100000 // i2c to hub -#define FREQ_I2C1_DEFAULT I2C_HZ // i2c to LED drivers -#define FREQ_TC45_DEFAULT 1000000 // 1 usec resolution +#define PLL_RATIO 47 // mcu frequency ((X+1)MHz) +#define FREQ_DFLL_DEFAULT 48000000 // DFLL frequency / usb clock +#define FREQ_SPI_DEFAULT 1000000 // spi to 595 shift regs +#define FREQ_I2C0_DEFAULT 100000 // i2c to hub +#define FREQ_I2C1_DEFAULT I2C_HZ // i2c to LED drivers +#define FREQ_TC45_DEFAULT 1000000 // 1 usec resolution // I2C1 Set ~Result PWM Time (2x Drivers) // 1000000 1090000 @@ -44,10 +44,10 @@ along with this program. If not, see . #define FREQ_XOSC0 16000000 -#define CHAN_SERCOM_SPI 2 // shift regs -#define CHAN_SERCOM_I2C0 0 // hub -#define CHAN_SERCOM_I2C1 1 // led drivers -#define CHAN_SERCOM_UART 3 // debug util +#define CHAN_SERCOM_SPI 2 // shift regs +#define CHAN_SERCOM_I2C0 0 // hub +#define CHAN_SERCOM_I2C1 1 // led drivers +#define CHAN_SERCOM_UART 3 // debug util // Generator clock channels #define GEN_DPLL0 0 @@ -86,4 +86,4 @@ uint32_t CLK_set_i2c0_freq(uint8_t sercomn, uint32_t freq); uint32_t CLK_set_i2c1_freq(uint8_t sercomn, uint32_t freq); void CLK_init(void); -#endif // _CLKS_H_ +#endif // _CLKS_H_ diff --git a/tmk_core/protocol/arm_atsam/d51_util.c b/tmk_core/protocol/arm_atsam/d51_util.c index df596f7ba2..5903233085 100644 --- a/tmk_core/protocol/arm_atsam/d51_util.c +++ b/tmk_core/protocol/arm_atsam/d51_util.c @@ -34,7 +34,8 @@ void dbg_print(uint32_t x) { while (t >= 0) { p2 = t; p = 1; - while (p2--) p *= 10; + while (p2--) + p *= 10; n = x / p; x -= n * p; if (!n) { @@ -55,7 +56,7 @@ void dbg_print(uint32_t x) { } for (w = DBG_PAUSE; w; w--) - ; // Long pause after number is complete + ; // Long pause after number is complete } // Display unsigned 32-bit number through debug led @@ -91,7 +92,8 @@ void dled_print(uint32_t x, uint8_t long_pause) { while (t >= 0) { p2 = t; p = 1; - while (p2--) p *= 10; + while (p2--) + p *= 10; n = x / p; x -= n * p; if (!n) { @@ -188,12 +190,12 @@ void debug_code_init(void) { DBGC(DC_UNSET); // Configure Ports for EIC - PORT->Group[DEBUG_BOOT_TRACING_PORT].DIRCLR.reg = 1 << DEBUG_BOOT_TRACING_PIN; // Input - PORT->Group[DEBUG_BOOT_TRACING_PORT].OUTSET.reg = 1 << DEBUG_BOOT_TRACING_PIN; // High - PORT->Group[DEBUG_BOOT_TRACING_PORT].PINCFG[DEBUG_BOOT_TRACING_PIN].bit.INEN = 1; // Input Enable - PORT->Group[DEBUG_BOOT_TRACING_PORT].PINCFG[DEBUG_BOOT_TRACING_PIN].bit.PULLEN = 1; // Pull Enable - PORT->Group[DEBUG_BOOT_TRACING_PORT].PINCFG[DEBUG_BOOT_TRACING_PIN].bit.PMUXEN = 1; // Mux Enable - PORT->Group[DEBUG_BOOT_TRACING_PORT].PMUX[DEBUG_BOOT_TRACING_PIN / 2].bit.PMUXO = 0; // Mux A + PORT->Group[DEBUG_BOOT_TRACING_PORT].DIRCLR.reg = 1 << DEBUG_BOOT_TRACING_PIN; // Input + PORT->Group[DEBUG_BOOT_TRACING_PORT].OUTSET.reg = 1 << DEBUG_BOOT_TRACING_PIN; // High + PORT->Group[DEBUG_BOOT_TRACING_PORT].PINCFG[DEBUG_BOOT_TRACING_PIN].bit.INEN = 1; // Input Enable + PORT->Group[DEBUG_BOOT_TRACING_PORT].PINCFG[DEBUG_BOOT_TRACING_PIN].bit.PULLEN = 1; // Pull Enable + PORT->Group[DEBUG_BOOT_TRACING_PORT].PINCFG[DEBUG_BOOT_TRACING_PIN].bit.PMUXEN = 1; // Mux Enable + PORT->Group[DEBUG_BOOT_TRACING_PORT].PMUX[DEBUG_BOOT_TRACING_PIN / 2].bit.PMUXO = 0; // Mux A // Enable CLK_EIC_APB MCLK->APBAMASK.bit.EIC_ = 1; @@ -223,12 +225,12 @@ void debug_code_disable(void) { } // Default port configuration - PORT->Group[DEBUG_BOOT_TRACING_PORT].DIRCLR.reg = 1 << DEBUG_BOOT_TRACING_PIN; // Input - PORT->Group[DEBUG_BOOT_TRACING_PORT].OUTCLR.reg = 1 << DEBUG_BOOT_TRACING_PIN; // Low - PORT->Group[DEBUG_BOOT_TRACING_PORT].PINCFG[DEBUG_BOOT_TRACING_PIN].bit.INEN = 0; // Input Disable - PORT->Group[DEBUG_BOOT_TRACING_PORT].PINCFG[DEBUG_BOOT_TRACING_PIN].bit.PULLEN = 0; // Pull Disable - PORT->Group[DEBUG_BOOT_TRACING_PORT].PINCFG[DEBUG_BOOT_TRACING_PIN].bit.PMUXEN = 0; // Mux Disable - PORT->Group[DEBUG_BOOT_TRACING_PORT].PMUX[DEBUG_BOOT_TRACING_PIN / 2].bit.PMUXO = 0; // Mux A + PORT->Group[DEBUG_BOOT_TRACING_PORT].DIRCLR.reg = 1 << DEBUG_BOOT_TRACING_PIN; // Input + PORT->Group[DEBUG_BOOT_TRACING_PORT].OUTCLR.reg = 1 << DEBUG_BOOT_TRACING_PIN; // Low + PORT->Group[DEBUG_BOOT_TRACING_PORT].PINCFG[DEBUG_BOOT_TRACING_PIN].bit.INEN = 0; // Input Disable + PORT->Group[DEBUG_BOOT_TRACING_PORT].PINCFG[DEBUG_BOOT_TRACING_PIN].bit.PULLEN = 0; // Pull Disable + PORT->Group[DEBUG_BOOT_TRACING_PORT].PINCFG[DEBUG_BOOT_TRACING_PIN].bit.PMUXEN = 0; // Mux Disable + PORT->Group[DEBUG_BOOT_TRACING_PORT].PMUX[DEBUG_BOOT_TRACING_PIN / 2].bit.PMUXO = 0; // Mux A // Disable CLK_EIC_APB MCLK->APBAMASK.bit.EIC_ = 0; @@ -239,4 +241,4 @@ void debug_code_disable(void) { void debug_code_init(void) {} void debug_code_disable(void) {} -#endif // DEBUG_BOOT_TRACING_ENABLE +#endif // DEBUG_BOOT_TRACING_ENABLE diff --git a/tmk_core/protocol/arm_atsam/d51_util.h b/tmk_core/protocol/arm_atsam/d51_util.h index 89cf338d23..d301e55411 100644 --- a/tmk_core/protocol/arm_atsam/d51_util.h +++ b/tmk_core/protocol/arm_atsam/d51_util.h @@ -219,6 +219,6 @@ enum debug_code_list { # define DBGC(n) \ {} -#endif // DEBUG_BOOT_TRACING_ENABLE +#endif // DEBUG_BOOT_TRACING_ENABLE -#endif //_D51_UTIL_H_ +#endif //_D51_UTIL_H_ diff --git a/tmk_core/protocol/arm_atsam/i2c_master.c b/tmk_core/protocol/arm_atsam/i2c_master.c index af046625f4..6b0b9a703b 100644 --- a/tmk_core/protocol/arm_atsam/i2c_master.c +++ b/tmk_core/protocol/arm_atsam/i2c_master.c @@ -26,21 +26,21 @@ along with this program. If not, see . # include "config_led.h" # include "matrix.h" -# define I2C_LED_USE_DMA 1 // Set 1 to use background DMA transfers for leds, Set 0 to use inline software transfers +# define I2C_LED_USE_DMA 1 // Set 1 to use background DMA transfers for leds, Set 0 to use inline software transfers DmacDescriptor dmac_desc; DmacDescriptor dmac_desc_wb; -static uint8_t i2c_led_q[I2C_Q_SIZE]; // I2C queue circular buffer -static uint8_t i2c_led_q_s; // Start of circular buffer -static uint8_t i2c_led_q_e; // End of circular buffer -static uint8_t i2c_led_q_full; // Queue full counter for reset +static uint8_t i2c_led_q[I2C_Q_SIZE]; // I2C queue circular buffer +static uint8_t i2c_led_q_s; // Start of circular buffer +static uint8_t i2c_led_q_e; // End of circular buffer +static uint8_t i2c_led_q_full; // Queue full counter for reset -static uint8_t dma_sendbuf[I2C_DMA_MAX_SEND]; // Data being written to I2C +static uint8_t dma_sendbuf[I2C_DMA_MAX_SEND]; // Data being written to I2C volatile uint8_t i2c_led_q_running; -#endif // !defined(MD_BOOTLOADER) && defined(RGB_MATRIX_ENABLE) +#endif // !defined(MD_BOOTLOADER) && defined(RGB_MATRIX_ENABLE) void i2c0_init(void) { DBGC(DC_I2C0_INIT_BEGIN); @@ -56,23 +56,23 @@ void i2c0_init(void) { // I2C // Note: SW Reset handled in CLK_set_i2c0_freq clks.c - SERCOM0->I2CM.CTRLA.bit.MODE = 5; // Set master mode + SERCOM0->I2CM.CTRLA.bit.MODE = 5; // Set master mode - SERCOM0->I2CM.CTRLA.bit.SPEED = 0; // Set to 1 for Fast-mode Plus (FM+) up to 1 MHz - SERCOM0->I2CM.CTRLA.bit.RUNSTDBY = 1; // Enabled + SERCOM0->I2CM.CTRLA.bit.SPEED = 0; // Set to 1 for Fast-mode Plus (FM+) up to 1 MHz + SERCOM0->I2CM.CTRLA.bit.RUNSTDBY = 1; // Enabled - SERCOM0->I2CM.CTRLA.bit.ENABLE = 1; // Enable the device + SERCOM0->I2CM.CTRLA.bit.ENABLE = 1; // Enable the device while (SERCOM0->I2CM.SYNCBUSY.bit.ENABLE) { DBGC(DC_I2C0_INIT_SYNC_ENABLING); - } // Wait for SYNCBUSY.ENABLE to clear + } // Wait for SYNCBUSY.ENABLE to clear - SERCOM0->I2CM.STATUS.bit.BUSSTATE = 1; // Force into IDLE state + SERCOM0->I2CM.STATUS.bit.BUSSTATE = 1; // Force into IDLE state while (SERCOM0->I2CM.SYNCBUSY.bit.SYSOP) { DBGC(DC_I2C0_INIT_SYNC_SYSOP); } while (SERCOM0->I2CM.STATUS.bit.BUSSTATE != 1) { DBGC(DC_I2C0_INIT_WAIT_IDLE); - } // Wait while not idle + } // Wait while not idle DBGC(DC_I2C0_INIT_COMPLETE); } @@ -139,27 +139,27 @@ void i2c1_init(void) { /* I2C */ // Note: SW Reset handled in CLK_set_i2c1_freq clks.c - SERCOM1->I2CM.CTRLA.bit.MODE = 5; // MODE: Set master mode (No sync) - SERCOM1->I2CM.CTRLA.bit.SPEED = 1; // SPEED: Fm+ up to 1MHz (No sync) - SERCOM1->I2CM.CTRLA.bit.RUNSTDBY = 1; // RUNSTBY: Enabled (No sync) + SERCOM1->I2CM.CTRLA.bit.MODE = 5; // MODE: Set master mode (No sync) + SERCOM1->I2CM.CTRLA.bit.SPEED = 1; // SPEED: Fm+ up to 1MHz (No sync) + SERCOM1->I2CM.CTRLA.bit.RUNSTDBY = 1; // RUNSTBY: Enabled (No sync) - SERCOM1->I2CM.CTRLB.bit.SMEN = 1; // SMEN: Smart mode enabled (For DMA)(No sync) + SERCOM1->I2CM.CTRLB.bit.SMEN = 1; // SMEN: Smart mode enabled (For DMA)(No sync) NVIC_EnableIRQ(SERCOM1_0_IRQn); SERCOM1->I2CM.INTENSET.bit.ERROR = 1; - SERCOM1->I2CM.CTRLA.bit.ENABLE = 1; // ENABLE: Enable the device (sync SYNCBUSY.ENABLE) + SERCOM1->I2CM.CTRLA.bit.ENABLE = 1; // ENABLE: Enable the device (sync SYNCBUSY.ENABLE) while (SERCOM1->I2CM.SYNCBUSY.bit.ENABLE) { DBGC(DC_I2C1_INIT_SYNC_ENABLING); - } // Wait for SYNCBUSY.ENABLE to clear + } // Wait for SYNCBUSY.ENABLE to clear - SERCOM1->I2CM.STATUS.bit.BUSSTATE = 1; // BUSSTATE: Force into IDLE state (sync SYNCBUSY.SYSOP) + SERCOM1->I2CM.STATUS.bit.BUSSTATE = 1; // BUSSTATE: Force into IDLE state (sync SYNCBUSY.SYSOP) while (SERCOM1->I2CM.SYNCBUSY.bit.SYSOP) { DBGC(DC_I2C1_INIT_SYNC_SYSOP); } while (SERCOM1->I2CM.STATUS.bit.BUSSTATE != 1) { DBGC(DC_I2C1_INIT_WAIT_IDLE); - } // Wait while not idle + } // Wait while not idle DBGC(DC_I2C1_INIT_COMPLETE); } @@ -240,7 +240,7 @@ void i2c_led_send_onoff(uint8_t drvid) { } # endif - *issidrv[drvid].onoff = 0; // Force start location offset to zero + *issidrv[drvid].onoff = 0; // Force start location offset to zero i2c1_transmit(issidrv[drvid].addr, issidrv[drvid].onoff, ISSI3733_PG0_BYTES, 0); } @@ -265,7 +265,7 @@ void i2c_led_send_pwm(uint8_t drvid) { } # endif - *issidrv[drvid].pwm = 0; // Force start location offset to zero + *issidrv[drvid].pwm = 0; // Force start location offset to zero i2c1_transmit(issidrv[drvid].addr, issidrv[drvid].pwm, ISSI3733_PG1_BYTES, 0); } @@ -300,12 +300,12 @@ uint8_t I2C3733_Init_Drivers(void) { // Set up master device i2c_led_send_CRWL(0); i2c_led_select_page(0, 3); - i2c_led_send_mode_op_gcr(0, 0, ISSI3733_CR_SSD_NORMAL); // No SYNC due to brightness mismatch with second driver + i2c_led_send_mode_op_gcr(0, 0, ISSI3733_CR_SSD_NORMAL); // No SYNC due to brightness mismatch with second driver // Set up slave device i2c_led_send_CRWL(1); i2c_led_select_page(1, 3); - i2c_led_send_mode_op_gcr(1, 0, ISSI3733_CR_SSD_NORMAL); // No SYNC due to brightness mismatch with first driver and slight flicker at rgb values 1,2 + i2c_led_send_mode_op_gcr(1, 0, ISSI3733_CR_SSD_NORMAL); // No SYNC due to brightness mismatch with first driver and slight flicker at rgb values 1,2 i2c_led_send_CRWL(0); i2c_led_select_page(0, 3); @@ -326,41 +326,41 @@ void I2C_DMAC_LED_Init(void) { DBGC(DC_I2C_DMAC_LED_INIT_BEGIN); // Disable device - dmac->CTRL.bit.DMAENABLE = 0; // Disable DMAC + dmac->CTRL.bit.DMAENABLE = 0; // Disable DMAC while (dmac->CTRL.bit.DMAENABLE) { - } // Wait for disabled state in case of ongoing transfers - dmac->CTRL.bit.SWRST = 1; // Software Reset DMAC + } // Wait for disabled state in case of ongoing transfers + dmac->CTRL.bit.SWRST = 1; // Software Reset DMAC while (dmac->CTRL.bit.SWRST) { - } // Wait for software reset to complete + } // Wait for software reset to complete // Configure device - dmac->BASEADDR.reg = (uint32_t)&dmac_desc; // Set descriptor base address - dmac->WRBADDR.reg = (uint32_t)&dmac_desc_wb; // Set descriptor write back address - dmac->CTRL.reg |= 0x0f00; // Handle all priorities (LVL0-3) + dmac->BASEADDR.reg = (uint32_t)&dmac_desc; // Set descriptor base address + dmac->WRBADDR.reg = (uint32_t)&dmac_desc_wb; // Set descriptor write back address + dmac->CTRL.reg |= 0x0f00; // Handle all priorities (LVL0-3) // Disable channel - dmac->Channel[0].CHCTRLA.bit.ENABLE = 0; // Disable the channel + dmac->Channel[0].CHCTRLA.bit.ENABLE = 0; // Disable the channel while (dmac->Channel[0].CHCTRLA.bit.ENABLE) { - } // Wait for disabled state in case of ongoing transfers - dmac->Channel[0].CHCTRLA.bit.SWRST = 1; // Software Reset the channel + } // Wait for disabled state in case of ongoing transfers + dmac->Channel[0].CHCTRLA.bit.SWRST = 1; // Software Reset the channel while (dmac->Channel[0].CHCTRLA.bit.SWRST) { - } // Wait for software reset to complete + } // Wait for software reset to complete // Configure channel - dmac->Channel[0].CHCTRLA.bit.THRESHOLD = 0; // 1BEAT - dmac->Channel[0].CHCTRLA.bit.BURSTLEN = 0; // SINGLE - dmac->Channel[0].CHCTRLA.bit.TRIGACT = 2; // BURST - dmac->Channel[0].CHCTRLA.bit.TRIGSRC = SERCOM1_DMAC_ID_TX; // Trigger source - dmac->Channel[0].CHCTRLA.bit.RUNSTDBY = 1; // Run in standby + dmac->Channel[0].CHCTRLA.bit.THRESHOLD = 0; // 1BEAT + dmac->Channel[0].CHCTRLA.bit.BURSTLEN = 0; // SINGLE + dmac->Channel[0].CHCTRLA.bit.TRIGACT = 2; // BURST + dmac->Channel[0].CHCTRLA.bit.TRIGSRC = SERCOM1_DMAC_ID_TX; // Trigger source + dmac->Channel[0].CHCTRLA.bit.RUNSTDBY = 1; // Run in standby NVIC_EnableIRQ(DMAC_0_IRQn); dmac->Channel[0].CHINTENSET.bit.TCMPL = 1; dmac->Channel[0].CHINTENSET.bit.TERR = 1; // Enable device - dmac->CTRL.bit.DMAENABLE = 1; // Enable DMAC + dmac->CTRL.bit.DMAENABLE = 1; // Enable DMAC while (dmac->CTRL.bit.DMAENABLE == 0) { - } // Wait for enable state + } // Wait for enable state DBGC(DC_I2C_DMAC_LED_INIT_COMPLETE); } @@ -377,14 +377,14 @@ void I2C3733_Control_Set(uint8_t state) { } void i2c_led_desc_defaults(void) { - dmac_desc.BTCTRL.bit.STEPSIZE = 0; // SRCINC used in favor for auto 1 inc - dmac_desc.BTCTRL.bit.STEPSEL = 0; // SRCINC used in favor for auto 1 inc - dmac_desc.BTCTRL.bit.DSTINC = 0; // The Destination Address Increment is disabled - dmac_desc.BTCTRL.bit.SRCINC = 1; // The Source Address Increment is enabled (Inc by 1) - dmac_desc.BTCTRL.bit.BEATSIZE = 0; // 8-bit bus transfer - dmac_desc.BTCTRL.bit.BLOCKACT = 0; // Channel will be disabled if it is the last block transfer in the transaction - dmac_desc.BTCTRL.bit.EVOSEL = 0; // Event generation disabled - dmac_desc.BTCTRL.bit.VALID = 1; // Set dmac valid + dmac_desc.BTCTRL.bit.STEPSIZE = 0; // SRCINC used in favor for auto 1 inc + dmac_desc.BTCTRL.bit.STEPSEL = 0; // SRCINC used in favor for auto 1 inc + dmac_desc.BTCTRL.bit.DSTINC = 0; // The Destination Address Increment is disabled + dmac_desc.BTCTRL.bit.SRCINC = 1; // The Source Address Increment is enabled (Inc by 1) + dmac_desc.BTCTRL.bit.BEATSIZE = 0; // 8-bit bus transfer + dmac_desc.BTCTRL.bit.BLOCKACT = 0; // Channel will be disabled if it is the last block transfer in the transaction + dmac_desc.BTCTRL.bit.EVOSEL = 0; // Event generation disabled + dmac_desc.BTCTRL.bit.VALID = 1; // Set dmac valid } void i2c_led_prepare_send_dma(uint8_t *data, uint8_t len) { @@ -397,9 +397,9 @@ void i2c_led_prepare_send_dma(uint8_t *data, uint8_t len) { } void i2c_led_begin_dma(uint8_t drvid) { - DMAC->Channel[0].CHCTRLA.bit.ENABLE = 1; // Enable the channel + DMAC->Channel[0].CHCTRLA.bit.ENABLE = 1; // Enable the channel - SERCOM1->I2CM.ADDR.reg = (dmac_desc.BTCNT.reg << 16) | 0x2000 | issidrv[drvid].addr; // Begin transfer + SERCOM1->I2CM.ADDR.reg = (dmac_desc.BTCNT.reg << 16) | 0x2000 | issidrv[drvid].addr; // Begin transfer } void i2c_led_send_CRWL_dma(uint8_t drvid) { @@ -429,7 +429,7 @@ void i2c_led_send_GCR_dma(uint8_t drvid) { void i2c_led_send_pwm_dma(uint8_t drvid) { // Note: This copies the CURRENT pwm buffer, which may be getting modified memcpy(dma_sendbuf, issidrv[drvid].pwm, ISSI3733_PG1_BYTES); - *dma_sendbuf = 0; // Force start location offset to zero + *dma_sendbuf = 0; // Force start location offset to zero i2c_led_prepare_send_dma(dma_sendbuf, ISSI3733_PG1_BYTES); i2c_led_begin_dma(drvid); @@ -438,7 +438,7 @@ void i2c_led_send_pwm_dma(uint8_t drvid) { void i2c_led_send_onoff_dma(uint8_t drvid) { // Note: This copies the CURRENT onoff buffer, which may be getting modified memcpy(dma_sendbuf, issidrv[drvid].onoff, ISSI3733_PG0_BYTES); - *dma_sendbuf = 0; // Force start location offset to zero + *dma_sendbuf = 0; // Force start location offset to zero i2c_led_prepare_send_dma(dma_sendbuf, ISSI3733_PG0_BYTES); i2c_led_begin_dma(drvid); @@ -452,12 +452,16 @@ void i2c_led_q_init(void) { i2c_led_q_full = 0; } -uint8_t i2c_led_q_isempty(void) { return i2c_led_q_s == i2c_led_q_e; } +uint8_t i2c_led_q_isempty(void) { + return i2c_led_q_s == i2c_led_q_e; +} -uint8_t i2c_led_q_size(void) { return (i2c_led_q_e - i2c_led_q_s) % I2C_Q_SIZE; } +uint8_t i2c_led_q_size(void) { + return (i2c_led_q_e - i2c_led_q_s) % I2C_Q_SIZE; +} uint8_t i2c_led_q_available(void) { - return I2C_Q_SIZE - i2c_led_q_size() - 1; // Never allow end to meet start + return I2C_Q_SIZE - i2c_led_q_size() - 1; // Never allow end to meet start } void i2c_led_q_add(uint8_t cmd) { @@ -466,11 +470,11 @@ void i2c_led_q_add(uint8_t cmd) { // Assign command i2c_led_q[i2c_led_q_e] = cmd; - i2c_led_q_e = (i2c_led_q_e + 1) % I2C_Q_SIZE; // Move end up one or wrap + i2c_led_q_e = (i2c_led_q_e + 1) % I2C_Q_SIZE; // Move end up one or wrap } void i2c_led_q_s_advance(void) { - i2c_led_q_s = (i2c_led_q_s + 1) % I2C_Q_SIZE; // Move start up one or wrap + i2c_led_q_s = (i2c_led_q_s + 1) % I2C_Q_SIZE; // Move start up one or wrap } // Always request room before adding commands @@ -480,7 +484,7 @@ uint8_t i2c_led_q_request_room(uint8_t request_size) { if (request_size > i2c_led_q_available()) { i2c_led_q_full++; - if (i2c_led_q_full >= 100) // Give the queue a chance to clear up + if (i2c_led_q_full >= 100) // Give the queue a chance to clear up { DBG_LED_ON; I2C_DMAC_LED_Init(); @@ -554,7 +558,7 @@ uint8_t i2c_led_q_run(void) { # endif } - i2c_led_q_s_advance(); // Advance last run command or if the command byte was not serviced + i2c_led_q_s_advance(); // Advance last run command or if the command byte was not serviced # if I2C_LED_USE_DMA != 1 } @@ -583,4 +587,4 @@ i2c_status_t i2c_transmit(uint8_t address, const uint8_t *data, uint16_t length, return ret ? I2C_STATUS_SUCCESS : I2C_STATUS_ERROR; } -#endif // !defined(MD_BOOTLOADER) && defined(RGB_MATRIX_ENABLE) +#endif // !defined(MD_BOOTLOADER) && defined(RGB_MATRIX_ENABLE) diff --git a/tmk_core/protocol/arm_atsam/i2c_master.h b/tmk_core/protocol/arm_atsam/i2c_master.h index e11235d447..5459923de4 100644 --- a/tmk_core/protocol/arm_atsam/i2c_master.h +++ b/tmk_core/protocol/arm_atsam/i2c_master.h @@ -95,7 +95,7 @@ void i2c1_init(void); uint8_t i2c1_transmit(uint8_t address, uint8_t *data, uint16_t length, uint16_t timeout); void i2c1_stop(void); -#endif // MD_BOOTLOADER +#endif // MD_BOOTLOADER void i2c0_init(void); uint8_t i2c0_transmit(uint8_t address, uint8_t *data, uint16_t length, uint16_t timeout); @@ -110,4 +110,4 @@ typedef int16_t i2c_status_t; void i2c_init(void); i2c_status_t i2c_transmit(uint8_t address, const uint8_t *data, uint16_t length, uint16_t timeout); -#endif // _I2C_MASTER_H_ +#endif // _I2C_MASTER_H_ diff --git a/tmk_core/protocol/arm_atsam/issi3733_driver.h b/tmk_core/protocol/arm_atsam/issi3733_driver.h index bd29fe76b6..c01f147e13 100644 --- a/tmk_core/protocol/arm_atsam/issi3733_driver.h +++ b/tmk_core/protocol/arm_atsam/issi3733_driver.h @@ -20,29 +20,29 @@ along with this program. If not, see . // ISII3733 Registers -#define ISSI3733_CMDR 0xFD // Command Register (Write Only) - -#define ISSI3733_CMDRWL 0xFE // Command Register Write Lock (Read/Write) -#define ISSI3733_CMDRWL_WRITE_DISABLE 0x00 // Lock register -#define ISSI3733_CMDRWL_WRITE_ENABLE_ONCE 0xC5 // Enable one write to register then reset to locked - -#define ISSI3733_IMR 0xF0 // Interrupt Mask Register (Write Only) -#define ISSI3733_IMR_IAC_ON 0x08 // Auto Clear Interrupt Bit - Interrupt auto clear when INTB stay low exceeds 8ms -#define ISSI3733_IMR_IAB_ON 0x04 // Auto Breath Interrupt Bit - Enable auto breath loop finish interrupt -#define ISSI3733_IMR_IS_ON 0x02 // Dot Short Interrupt Bit - Enable dot short interrupt -#define ISSI3733_IMR_IO_ON 0x01 // Dot Open Interrupt Bit - Enable dot open interrupt - -#define ISSI3733_ISR 0xF1 // Interrupt Status Register (Read Only) -#define ISSI3733_ISR_ABM3_FINISH 0x10 // Auto Breath Mode 3 Finish Bit - ABM3 finished -#define ISSI3733_ISR_ABM2_FINISH 0x08 // Auto Breath Mode 2 Finish Bit - ABM2 finished -#define ISSI3733_ISR_ABM1_FINISH 0x04 // Auto Breath Mode 1 Finish Bit - ABM1 finished -#define ISSI3733_ISR_SB 0x02 // Short Bit - Shorted -#define ISSI3733_ISR_OB 0x01 // Open Bit - Opened - -#define ISSI3733_PG0 0x00 // LED Control Register -#define ISSI3733_PG1 0x01 // PWM Register -#define ISSI3733_PG2 0x02 // Auto Breath Mode Register -#define ISSI3733_PG3 0x03 // Function Register +#define ISSI3733_CMDR 0xFD // Command Register (Write Only) + +#define ISSI3733_CMDRWL 0xFE // Command Register Write Lock (Read/Write) +#define ISSI3733_CMDRWL_WRITE_DISABLE 0x00 // Lock register +#define ISSI3733_CMDRWL_WRITE_ENABLE_ONCE 0xC5 // Enable one write to register then reset to locked + +#define ISSI3733_IMR 0xF0 // Interrupt Mask Register (Write Only) +#define ISSI3733_IMR_IAC_ON 0x08 // Auto Clear Interrupt Bit - Interrupt auto clear when INTB stay low exceeds 8ms +#define ISSI3733_IMR_IAB_ON 0x04 // Auto Breath Interrupt Bit - Enable auto breath loop finish interrupt +#define ISSI3733_IMR_IS_ON 0x02 // Dot Short Interrupt Bit - Enable dot short interrupt +#define ISSI3733_IMR_IO_ON 0x01 // Dot Open Interrupt Bit - Enable dot open interrupt + +#define ISSI3733_ISR 0xF1 // Interrupt Status Register (Read Only) +#define ISSI3733_ISR_ABM3_FINISH 0x10 // Auto Breath Mode 3 Finish Bit - ABM3 finished +#define ISSI3733_ISR_ABM2_FINISH 0x08 // Auto Breath Mode 2 Finish Bit - ABM2 finished +#define ISSI3733_ISR_ABM1_FINISH 0x04 // Auto Breath Mode 1 Finish Bit - ABM1 finished +#define ISSI3733_ISR_SB 0x02 // Short Bit - Shorted +#define ISSI3733_ISR_OB 0x01 // Open Bit - Opened + +#define ISSI3733_PG0 0x00 // LED Control Register +#define ISSI3733_PG1 0x01 // PWM Register +#define ISSI3733_PG2 0x02 // Auto Breath Mode Register +#define ISSI3733_PG3 0x03 // Function Register #define ISSI3733_PG_ONOFF ISSI3733_PG0 #define ISSI3733_PG_OR ISSI3733_PG0 @@ -51,88 +51,88 @@ along with this program. If not, see . #define ISSI3733_PG_ABM ISSI3733_PG2 #define ISSI3733_PG_FN ISSI3733_PG3 -#define ISSI3733_CR 0x00 // Configuration Register +#define ISSI3733_CR 0x00 // Configuration Register // PG3: Configuration Register: Synchronize Configuration -#define ISSI3733_CR_SYNC_MASTER 0x40 // Master -#define ISSI3733_CR_SYNC_SLAVE 0x80 // Slave -#define ISSI3733_CR_SYNC_HIGH_IMP 0xC0 // High Impedance +#define ISSI3733_CR_SYNC_MASTER 0x40 // Master +#define ISSI3733_CR_SYNC_SLAVE 0x80 // Slave +#define ISSI3733_CR_SYNC_HIGH_IMP 0xC0 // High Impedance // PG3: Configuration Register: Open/Short Detection Enable Bit //#define ISSI3733_CR_OSD_DISABLE 0x00 //Disable open/short detection -#define ISSI3733_CR_OSD_ENABLE 0x04 // Enable open/short detection +#define ISSI3733_CR_OSD_ENABLE 0x04 // Enable open/short detection // PG3: Configuration Register: Auto Breath Enable //#define ISSI3733_CR_B_EN_PWM 0x00 //PWM Mode Enable -#define ISSI3733_CR_B_EN_AUTO 0x02 // Auto Breath Mode Enable +#define ISSI3733_CR_B_EN_AUTO 0x02 // Auto Breath Mode Enable // PG3: Configuration Register: Software Shutdown Control //#define ISSI3733_CR_SSD_SHUTDOWN 0x00 //Software shutdown -#define ISSI3733_CR_SSD_NORMAL 0x01 // Normal operation +#define ISSI3733_CR_SSD_NORMAL 0x01 // Normal operation -#define ISSI3733_GCCR 0x01 // Global Current Control Register +#define ISSI3733_GCCR 0x01 // Global Current Control Register // 1 Byte, Iout = (GCC / 256) * (840 / Rext) // TODO: Give user define for Rext // PG3: Auto Breath Control Register 1 -#define ISSI3733_ABCR1_ABM1 0x02 // Auto Breath Control Register 1 of ABM-1 -#define ISSI3733_ABCR1_ABM2 0x06 // Auto Breath Control Register 1 of ABM-2 -#define ISSI3733_ABCR1_ABM3 0x0A // Auto Breath Control Register 1 of ABM-3 +#define ISSI3733_ABCR1_ABM1 0x02 // Auto Breath Control Register 1 of ABM-1 +#define ISSI3733_ABCR1_ABM2 0x06 // Auto Breath Control Register 1 of ABM-2 +#define ISSI3733_ABCR1_ABM3 0x0A // Auto Breath Control Register 1 of ABM-3 // Rise time -#define ISSI3733_ABCR1_T1_0021 0x00 // 0.21s -#define ISSI3733_ABCR1_T1_0042 0x20 // 0.42s -#define ISSI3733_ABCR1_T1_0084 0x40 // 0.84s -#define ISSI3733_ABCR1_T1_0168 0x60 // 1.68s -#define ISSI3733_ABCR1_T1_0336 0x80 // 3.36s -#define ISSI3733_ABCR1_T1_0672 0xA0 // 6.72s -#define ISSI3733_ABCR1_T1_1344 0xC0 // 13.44s -#define ISSI3733_ABCR1_T1_2688 0xE0 // 26.88s +#define ISSI3733_ABCR1_T1_0021 0x00 // 0.21s +#define ISSI3733_ABCR1_T1_0042 0x20 // 0.42s +#define ISSI3733_ABCR1_T1_0084 0x40 // 0.84s +#define ISSI3733_ABCR1_T1_0168 0x60 // 1.68s +#define ISSI3733_ABCR1_T1_0336 0x80 // 3.36s +#define ISSI3733_ABCR1_T1_0672 0xA0 // 6.72s +#define ISSI3733_ABCR1_T1_1344 0xC0 // 13.44s +#define ISSI3733_ABCR1_T1_2688 0xE0 // 26.88s // Max value time -#define ISSI3733_ABCR1_T2_0000 0x00 // 0s -#define ISSI3733_ABCR1_T2_0021 0x02 // 0.21s -#define ISSI3733_ABCR1_T2_0042 0x04 // 0.42s -#define ISSI3733_ABCR1_T2_0084 0x06 // 0.84s -#define ISSI3733_ABCR1_T2_0168 0x08 // 1.68s -#define ISSI3733_ABCR1_T2_0336 0x0A // 3.36s -#define ISSI3733_ABCR1_T2_0672 0x0C // 6.72s -#define ISSI3733_ABCR1_T2_1344 0x0E // 13.44s -#define ISSI3733_ABCR1_T2_2688 0x10 // 26.88s +#define ISSI3733_ABCR1_T2_0000 0x00 // 0s +#define ISSI3733_ABCR1_T2_0021 0x02 // 0.21s +#define ISSI3733_ABCR1_T2_0042 0x04 // 0.42s +#define ISSI3733_ABCR1_T2_0084 0x06 // 0.84s +#define ISSI3733_ABCR1_T2_0168 0x08 // 1.68s +#define ISSI3733_ABCR1_T2_0336 0x0A // 3.36s +#define ISSI3733_ABCR1_T2_0672 0x0C // 6.72s +#define ISSI3733_ABCR1_T2_1344 0x0E // 13.44s +#define ISSI3733_ABCR1_T2_2688 0x10 // 26.88s // PG3: Auto Breath Control Register 2 -#define ISSI3733_ABCR2_ABM1 0x03 // Auto Breath Control Register 2 of ABM-1 -#define ISSI3733_ABCR2_ABM2 0x07 // Auto Breath Control Register 2 of ABM-2 -#define ISSI3733_ABCR2_ABM3 0x0B // Auto Breath Control Register 2 of ABM-3 +#define ISSI3733_ABCR2_ABM1 0x03 // Auto Breath Control Register 2 of ABM-1 +#define ISSI3733_ABCR2_ABM2 0x07 // Auto Breath Control Register 2 of ABM-2 +#define ISSI3733_ABCR2_ABM3 0x0B // Auto Breath Control Register 2 of ABM-3 // Fall time -#define ISSI3733_ABCR2_T3_0021 0x00 // 0.21s -#define ISSI3733_ABCR2_T3_0042 0x20 // 0.42s -#define ISSI3733_ABCR2_T3_0084 0x40 // 0.84s -#define ISSI3733_ABCR2_T3_0168 0x60 // 1.68s -#define ISSI3733_ABCR2_T3_0336 0x80 // 3.36s -#define ISSI3733_ABCR2_T3_0672 0xA0 // 6.72s -#define ISSI3733_ABCR2_T3_1344 0xC0 // 13.44s -#define ISSI3733_ABCR2_T3_2688 0xE0 // 26.88s +#define ISSI3733_ABCR2_T3_0021 0x00 // 0.21s +#define ISSI3733_ABCR2_T3_0042 0x20 // 0.42s +#define ISSI3733_ABCR2_T3_0084 0x40 // 0.84s +#define ISSI3733_ABCR2_T3_0168 0x60 // 1.68s +#define ISSI3733_ABCR2_T3_0336 0x80 // 3.36s +#define ISSI3733_ABCR2_T3_0672 0xA0 // 6.72s +#define ISSI3733_ABCR2_T3_1344 0xC0 // 13.44s +#define ISSI3733_ABCR2_T3_2688 0xE0 // 26.88s // Min value time -#define ISSI3733_ABCR2_T4_0000 0x00 // 0s -#define ISSI3733_ABCR2_T4_0021 0x02 // 0.21s -#define ISSI3733_ABCR2_T4_0042 0x04 // 0.42s -#define ISSI3733_ABCR2_T4_0084 0x06 // 0.84s -#define ISSI3733_ABCR2_T4_0168 0x08 // 1.68s -#define ISSI3733_ABCR2_T4_0336 0x0A // 3.36s -#define ISSI3733_ABCR2_T4_0672 0x0C // 6.72s -#define ISSI3733_ABCR2_T4_1344 0x0E // 13.44s -#define ISSI3733_ABCR2_T4_2688 0x10 // 26.88s -#define ISSI3733_ABCR2_T4_5376 0x12 // 53.76s -#define ISSI3733_ABCR2_T4_10752 0x14 // 107.52s +#define ISSI3733_ABCR2_T4_0000 0x00 // 0s +#define ISSI3733_ABCR2_T4_0021 0x02 // 0.21s +#define ISSI3733_ABCR2_T4_0042 0x04 // 0.42s +#define ISSI3733_ABCR2_T4_0084 0x06 // 0.84s +#define ISSI3733_ABCR2_T4_0168 0x08 // 1.68s +#define ISSI3733_ABCR2_T4_0336 0x0A // 3.36s +#define ISSI3733_ABCR2_T4_0672 0x0C // 6.72s +#define ISSI3733_ABCR2_T4_1344 0x0E // 13.44s +#define ISSI3733_ABCR2_T4_2688 0x10 // 26.88s +#define ISSI3733_ABCR2_T4_5376 0x12 // 53.76s +#define ISSI3733_ABCR2_T4_10752 0x14 // 107.52s // PG3: Auto Breath Control Register 3 -#define ISSI3733_ABCR3_ABM1 0x04 // Auto Breath Control Register 3 of ABM-1 -#define ISSI3733_ABCR3_ABM2 0x08 // Auto Breath Control Register 3 of ABM-2 -#define ISSI3733_ABCR3_ABM3 0x0C // Auto Breath Control Register 3 of ABM-3 +#define ISSI3733_ABCR3_ABM1 0x04 // Auto Breath Control Register 3 of ABM-1 +#define ISSI3733_ABCR3_ABM2 0x08 // Auto Breath Control Register 3 of ABM-2 +#define ISSI3733_ABCR3_ABM3 0x0C // Auto Breath Control Register 3 of ABM-3 #define ISSI3733_ABCR3_LTA_LOOP_ENDLESS 0x00 #define ISSI3733_ABCR3_LTA_LOOP_1 0x01 @@ -158,44 +158,44 @@ along with this program. If not, see . #define ISSI3733_ABCR3_LB_T4 0x30 // Loop End -#define ISSI3733_ABCR3_LE_T3 0x00 // End at Off state -#define ISSI3733_ABCR3_LE_T1 0x40 // End at On State +#define ISSI3733_ABCR3_LE_T3 0x00 // End at Off state +#define ISSI3733_ABCR3_LE_T1 0x40 // End at On State // PG3: Auto Breath Control Register 4 -#define ISSI3733_ABCR4_ABM1 0x05 // Auto Breath Control Register 4 of ABM-1 -#define ISSI3733_ABCR4_ABM2 0x09 // Auto Breath Control Register 4 of ABM-2 -#define ISSI3733_ABCR4_ABM3 0x0D // Auto Breath Control Register 4 of ABM-3 +#define ISSI3733_ABCR4_ABM1 0x05 // Auto Breath Control Register 4 of ABM-1 +#define ISSI3733_ABCR4_ABM2 0x09 // Auto Breath Control Register 4 of ABM-2 +#define ISSI3733_ABCR4_ABM3 0x0D // Auto Breath Control Register 4 of ABM-3 #define ISSI3733_ABCR4_LTB_LOOP_ENDLESS 0x00 // Or 8bit loop times // PG3: Time Update Register #define ISSI3733_TUR 0x0E -#define ISSI3733_TUR_UPDATE 0x00 // Write to update 02h~0Dh time registers after configuring +#define ISSI3733_TUR_UPDATE 0x00 // Write to update 02h~0Dh time registers after configuring // PG3: SWy Pull-Up Resistor Selection Register #define ISSI3733_SWYR_PUR 0x0F -#define ISSI3733_SWYR_PUR_NONE 0x00 // No pull-up resistor -#define ISSI3733_SWYR_PUR_500 0x01 // 0.5k Ohm -#define ISSI3733_SWYR_PUR_1000 0x02 // 1.0k Ohm -#define ISSI3733_SWYR_PUR_2000 0x03 // 2.0k Ohm -#define ISSI3733_SWYR_PUR_4000 0x04 // 4.0k Ohm -#define ISSI3733_SWYR_PUR_8000 0x05 // 8.0k Ohm -#define ISSI3733_SWYR_PUR_16000 0x06 // 16k Ohm -#define ISSI3733_SWYR_PUR_32000 0x07 // 32k Ohm +#define ISSI3733_SWYR_PUR_NONE 0x00 // No pull-up resistor +#define ISSI3733_SWYR_PUR_500 0x01 // 0.5k Ohm +#define ISSI3733_SWYR_PUR_1000 0x02 // 1.0k Ohm +#define ISSI3733_SWYR_PUR_2000 0x03 // 2.0k Ohm +#define ISSI3733_SWYR_PUR_4000 0x04 // 4.0k Ohm +#define ISSI3733_SWYR_PUR_8000 0x05 // 8.0k Ohm +#define ISSI3733_SWYR_PUR_16000 0x06 // 16k Ohm +#define ISSI3733_SWYR_PUR_32000 0x07 // 32k Ohm // PG3: CSx Pull-Down Resistor Selection Register #define ISSI3733_CSXR_PDR 0x10 -#define ISSI3733_CSXR_PDR_NONE 0x00 // No pull-down resistor -#define ISSI3733_CSXR_PDR_500 0x01 // 0.5k Ohm -#define ISSI3733_CSXR_PDR_1000 0x02 // 1.0k Ohm -#define ISSI3733_CSXR_PDR_2000 0x03 // 2.0k Ohm -#define ISSI3733_CSXR_PDR_4000 0x04 // 4.0k Ohm -#define ISSI3733_CSXR_PDR_8000 0x05 // 8.0k Ohm -#define ISSI3733_CSXR_PDR_16000 0x06 // 16k Ohm -#define ISSI3733_CSXR_PDR_32000 0x07 // 32k Ohm +#define ISSI3733_CSXR_PDR_NONE 0x00 // No pull-down resistor +#define ISSI3733_CSXR_PDR_500 0x01 // 0.5k Ohm +#define ISSI3733_CSXR_PDR_1000 0x02 // 1.0k Ohm +#define ISSI3733_CSXR_PDR_2000 0x03 // 2.0k Ohm +#define ISSI3733_CSXR_PDR_4000 0x04 // 4.0k Ohm +#define ISSI3733_CSXR_PDR_8000 0x05 // 8.0k Ohm +#define ISSI3733_CSXR_PDR_16000 0x06 // 16k Ohm +#define ISSI3733_CSXR_PDR_32000 0x07 // 32k Ohm // PG3: Reset Register -#define ISSI3733_RR 0x11 // Read to reset all registers to default values +#define ISSI3733_RR 0x11 // Read to reset all registers to default values -#endif //_ISSI3733_DRIVER_H_ +#endif //_ISSI3733_DRIVER_H_ diff --git a/tmk_core/protocol/arm_atsam/main_arm_atsam.c b/tmk_core/protocol/arm_atsam/main_arm_atsam.c index de12821a74..d092da8682 100644 --- a/tmk_core/protocol/arm_atsam/main_arm_atsam.c +++ b/tmk_core/protocol/arm_atsam/main_arm_atsam.c @@ -31,7 +31,7 @@ along with this program. If not, see . // From keyboard's directory #include "config_led.h" -uint8_t g_usb_state = USB_FSMSTATUS_FSMSTATE_OFF_Val; // Saved USB state from hardware value to detect changes +uint8_t g_usb_state = USB_FSMSTATUS_FSMSTATE_OFF_Val; // Saved USB state from hardware value to detect changes void main_subtasks(void); uint8_t keyboard_leds(void); @@ -42,7 +42,7 @@ void send_consumer(uint16_t data); #ifdef DEFERRED_EXEC_ENABLE void deferred_exec_task(void); -#endif // DEFERRED_EXEC_ENABLE +#endif // DEFERRED_EXEC_ENABLE host_driver_t arm_atsam_driver = {keyboard_leds, send_keyboard, send_mouse, send_system, send_consumer}; @@ -53,7 +53,7 @@ uint8_t keyboard_leds(void) { if (keymap_config.nkro) return udi_hid_nkro_report_set; else -#endif // NKRO_ENABLE +#endif // NKRO_ENABLE return udi_hid_kbd_report_set; } @@ -62,10 +62,10 @@ void send_keyboard(report_keyboard_t *report) { #ifdef NKRO_ENABLE if (!keymap_config.nkro) { -#endif // NKRO_ENABLE +#endif // NKRO_ENABLE while (udi_hid_kbd_b_report_trans_ongoing) { main_subtasks(); - } // Run other tasks while waiting for USB to be free + } // Run other tasks while waiting for USB to be free irqflags = __get_PRIMASK(); __disable_irq(); @@ -81,7 +81,7 @@ void send_keyboard(report_keyboard_t *report) { } else { while (udi_hid_nkro_b_report_trans_ongoing) { main_subtasks(); - } // Run other tasks while waiting for USB to be free + } // Run other tasks while waiting for USB to be free irqflags = __get_PRIMASK(); __disable_irq(); @@ -94,7 +94,7 @@ void send_keyboard(report_keyboard_t *report) { __DMB(); __set_PRIMASK(irqflags); } -#endif // NKRO_ENABLE +#endif // NKRO_ENABLE } void send_mouse(report_mouse_t *report) { @@ -111,7 +111,7 @@ void send_mouse(report_mouse_t *report) { __DMB(); __set_PRIMASK(irqflags); -#endif // MOUSEKEY_ENABLE +#endif // MOUSEKEY_ENABLE } #ifdef EXTRAKEY_ENABLE @@ -130,18 +130,18 @@ void send_extra(uint8_t report_id, uint16_t data) { __DMB(); __set_PRIMASK(irqflags); } -#endif // EXTRAKEY_ENABLE +#endif // EXTRAKEY_ENABLE void send_system(uint16_t data) { #ifdef EXTRAKEY_ENABLE send_extra(REPORT_ID_SYSTEM, data); -#endif // EXTRAKEY_ENABLE +#endif // EXTRAKEY_ENABLE } void send_consumer(uint16_t data) { #ifdef EXTRAKEY_ENABLE send_extra(REPORT_ID_CONSUMER, data); -#endif // EXTRAKEY_ENABLE +#endif // EXTRAKEY_ENABLE } #ifdef CONSOLE_ENABLE @@ -158,81 +158,81 @@ int8_t sendchar(uint8_t c) { void main_subtask_console_flush(void) { while (udi_hid_con_b_report_trans_ongoing) { - } // Wait for any previous transfers to complete + } // Wait for any previous transfers to complete uint16_t result = console_printbuf_len; uint32_t irqflags; - char * pconbuf = console_printbuf; // Pointer to start send from - int send_out = CONSOLE_EPSIZE; // Bytes to send per transfer + char * pconbuf = console_printbuf; // Pointer to start send from + int send_out = CONSOLE_EPSIZE; // Bytes to send per transfer - while (result > 0) { // While not error and bytes remain + while (result > 0) { // While not error and bytes remain while (udi_hid_con_b_report_trans_ongoing) { - } // Wait for any previous transfers to complete + } // Wait for any previous transfers to complete irqflags = __get_PRIMASK(); __disable_irq(); __DMB(); - if (result < CONSOLE_EPSIZE) { // If remaining bytes are less than console epsize - memset(udi_hid_con_report, 0, CONSOLE_EPSIZE); // Clear the buffer - send_out = result; // Send remaining size + if (result < CONSOLE_EPSIZE) { // If remaining bytes are less than console epsize + memset(udi_hid_con_report, 0, CONSOLE_EPSIZE); // Clear the buffer + send_out = result; // Send remaining size } - memcpy(udi_hid_con_report, pconbuf, send_out); // Copy data into the send buffer + memcpy(udi_hid_con_report, pconbuf, send_out); // Copy data into the send buffer - udi_hid_con_b_report_valid = 1; // Set report valid - udi_hid_con_send_report(); // Send report + udi_hid_con_b_report_valid = 1; // Set report valid + udi_hid_con_send_report(); // Send report __DMB(); __set_PRIMASK(irqflags); - result -= send_out; // Decrement result by bytes sent - pconbuf += send_out; // Increment buffer point by bytes sent + result -= send_out; // Decrement result by bytes sent + pconbuf += send_out; // Increment buffer point by bytes sent } console_printbuf_len = 0; } -#endif // CONSOLE_ENABLE +#endif // CONSOLE_ENABLE void main_subtask_usb_state(void) { - static uint64_t fsmstate_on_delay = 0; // Delay timer to be sure USB is actually operating before bringing up hardware - uint8_t fsmstate_now = USB->DEVICE.FSMSTATUS.reg; // Current state from hardware register + static uint64_t fsmstate_on_delay = 0; // Delay timer to be sure USB is actually operating before bringing up hardware + uint8_t fsmstate_now = USB->DEVICE.FSMSTATUS.reg; // Current state from hardware register - if (fsmstate_now == USB_FSMSTATUS_FSMSTATE_SUSPEND_Val) // If USB SUSPENDED + if (fsmstate_now == USB_FSMSTATUS_FSMSTATE_SUSPEND_Val) // If USB SUSPENDED { - fsmstate_on_delay = 0; // Clear ON delay timer + fsmstate_on_delay = 0; // Clear ON delay timer - if (g_usb_state != USB_FSMSTATUS_FSMSTATE_SUSPEND_Val) // If previously not SUSPENDED + if (g_usb_state != USB_FSMSTATUS_FSMSTATE_SUSPEND_Val) // If previously not SUSPENDED { - suspend_power_down(); // Run suspend routine - g_usb_state = fsmstate_now; // Save current USB state + suspend_power_down(); // Run suspend routine + g_usb_state = fsmstate_now; // Save current USB state } - } else if (fsmstate_now == USB_FSMSTATUS_FSMSTATE_SLEEP_Val) // Else if USB SLEEPING + } else if (fsmstate_now == USB_FSMSTATUS_FSMSTATE_SLEEP_Val) // Else if USB SLEEPING { - fsmstate_on_delay = 0; // Clear ON delay timer + fsmstate_on_delay = 0; // Clear ON delay timer - if (g_usb_state != USB_FSMSTATUS_FSMSTATE_SLEEP_Val) // If previously not SLEEPING + if (g_usb_state != USB_FSMSTATUS_FSMSTATE_SLEEP_Val) // If previously not SLEEPING { - suspend_power_down(); // Run suspend routine - g_usb_state = fsmstate_now; // Save current USB state + suspend_power_down(); // Run suspend routine + g_usb_state = fsmstate_now; // Save current USB state } - } else if (fsmstate_now == USB_FSMSTATUS_FSMSTATE_ON_Val) // Else if USB ON + } else if (fsmstate_now == USB_FSMSTATUS_FSMSTATE_ON_Val) // Else if USB ON { - if (g_usb_state != USB_FSMSTATUS_FSMSTATE_ON_Val) // If previously not ON + if (g_usb_state != USB_FSMSTATUS_FSMSTATE_ON_Val) // If previously not ON { - if (fsmstate_on_delay == 0) // If ON delay timer is cleared + if (fsmstate_on_delay == 0) // If ON delay timer is cleared { - fsmstate_on_delay = timer_read64() + 250; // Set ON delay timer - } else if (timer_read64() > fsmstate_on_delay) // Else if ON delay timer is active and timed out + fsmstate_on_delay = timer_read64() + 250; // Set ON delay timer + } else if (timer_read64() > fsmstate_on_delay) // Else if ON delay timer is active and timed out { - suspend_wakeup_init(); // Run wakeup routine - g_usb_state = fsmstate_now; // Save current USB state + suspend_wakeup_init(); // Run wakeup routine + g_usb_state = fsmstate_now; // Save current USB state } } - } else // Else if USB is in a state not being tracked + } else // Else if USB is in a state not being tracked { - fsmstate_on_delay = 0; // Clear ON delay timer + fsmstate_on_delay = 0; // Clear ON delay timer } } @@ -262,7 +262,9 @@ void main_subtask_usb_extra_device(void) { } #ifdef RAW_ENABLE -void main_subtask_raw(void) { udi_hid_raw_receive_report(); } +void main_subtask_raw(void) { + udi_hid_raw_receive_report(); +} #endif void main_subtasks(void) { @@ -296,7 +298,7 @@ int main(void) { #ifdef RGB_MATRIX_ENABLE i2c1_init(); -#endif // RGB_MATRIX_ENABLE +#endif // RGB_MATRIX_ENABLE matrix_init(); @@ -325,8 +327,9 @@ int main(void) { i2c_led_q_init(); - for (uint8_t drvid = 0; drvid < ISSI3733_DRIVER_COUNT; drvid++) I2C_LED_Q_ONOFF(drvid); // Queue data -#endif // RGB_MATRIX_ENABLE + for (uint8_t drvid = 0; drvid < ISSI3733_DRIVER_COUNT; drvid++) + I2C_LED_Q_ONOFF(drvid); // Queue data +#endif // RGB_MATRIX_ENABLE keyboard_setup(); @@ -336,18 +339,18 @@ int main(void) { #ifdef CONSOLE_ENABLE uint64_t next_print = 0; -#endif // CONSOLE_ENABLE +#endif // CONSOLE_ENABLE v_5v_avg = adc_get(ADC_5V); debug_code_disable(); while (1) { - main_subtasks(); // Note these tasks will also be run while waiting for USB keyboard polling intervals + main_subtasks(); // Note these tasks will also be run while waiting for USB keyboard polling intervals if (g_usb_state == USB_FSMSTATUS_FSMSTATE_SUSPEND_Val || g_usb_state == USB_FSMSTATUS_FSMSTATE_SLEEP_Val) { if (suspend_wakeup_condition()) { - udc_remotewakeup(); // Send remote wakeup signal + udc_remotewakeup(); // Send remote wakeup signal wait_ms(50); } @@ -362,12 +365,12 @@ int main(void) { // Add any debug information here that you want to see very often // dprintf("5v=%u 5vu=%u dlow=%u dhi=%u gca=%u gcd=%u\r\n", v_5v, v_5v_avg, v_5v_avg - V5_LOW, v_5v_avg - V5_HIGH, gcr_actual, gcr_desired); } -#endif // CONSOLE_ENABLE +#endif // CONSOLE_ENABLE #ifdef DEFERRED_EXEC_ENABLE // Run deferred executions deferred_exec_task(); -#endif // DEFERRED_EXEC_ENABLE +#endif // DEFERRED_EXEC_ENABLE // Run housekeeping housekeeping_task(); diff --git a/tmk_core/protocol/arm_atsam/main_arm_atsam.h b/tmk_core/protocol/arm_atsam/main_arm_atsam.h index 5b088f0e20..78205e2e1b 100644 --- a/tmk_core/protocol/arm_atsam/main_arm_atsam.h +++ b/tmk_core/protocol/arm_atsam/main_arm_atsam.h @@ -20,4 +20,4 @@ along with this program. If not, see . uint8_t keyboard_leds(void); -#endif //_MAIN_ARM_ATSAM_H_ +#endif //_MAIN_ARM_ATSAM_H_ diff --git a/tmk_core/protocol/arm_atsam/md_rgb_matrix.c b/tmk_core/protocol/arm_atsam/md_rgb_matrix.c index 0741584439..84ce3ee24b 100644 --- a/tmk_core/protocol/arm_atsam/md_rgb_matrix.c +++ b/tmk_core/protocol/arm_atsam/md_rgb_matrix.c @@ -53,16 +53,20 @@ void eeconfig_update_md_led_default(void) { eeconfig_flush_md_led(true); } -void md_led_changed(void) { eeconfig_flag_md_led(true); } +void md_led_changed(void) { + eeconfig_flag_md_led(true); +} // todo: use real task rather than this bodge -void housekeeping_task_kb(void) { eeconfig_flush_md_led_task(FLUSH_TIMEOUT); } +void housekeeping_task_kb(void) { + eeconfig_flush_md_led_task(FLUSH_TIMEOUT); +} __attribute__((weak)) led_instruction_t led_instructions[] = {{.end = 1}}; static void md_rgb_matrix_config_override(int i); # else uint8_t gcr_desired; -# endif // USE_MASSDROP_CONFIGURATOR +# endif // USE_MASSDROP_CONFIGURATOR void SERCOM1_0_Handler(void) { if (SERCOM1->I2CM.INTFLAG.bit.ERROR) { @@ -125,9 +129,9 @@ void gcr_compute(void) { if (v_5v < V5_CAT) { I2C3733_Control_Set(0); // CDC_print("USB: WARNING: 5V catastrophic level reached! Disabling LED drivers!\r\n"); //Blocking print is bad here! - v_5v_cat_hit = 20; //~100ms recover - gcr_actual = 0; // Minimize GCR - usb_gcr_auto = 1; // Force auto mode enabled + v_5v_cat_hit = 20; //~100ms recover + gcr_actual = 0; // Minimize GCR + usb_gcr_auto = 1; // Force auto mode enabled return; } else if (v_5v_cat_hit > 1) { v_5v_cat_hit--; @@ -157,24 +161,24 @@ void gcr_compute(void) { gcr_min_counter = 0; } else if (action == ACT_GCR_INC) { if (LED_GCR_STEP_AUTO > LED_GCR_MAX - gcr_actual) - gcr_actual = LED_GCR_MAX; // Obey max and prevent wrapping + gcr_actual = LED_GCR_MAX; // Obey max and prevent wrapping else gcr_actual += LED_GCR_STEP_AUTO; gcr_min_counter = 0; } else if (action == ACT_GCR_DEC) { - if (LED_GCR_STEP_AUTO > gcr_actual) // Prevent wrapping + if (LED_GCR_STEP_AUTO > gcr_actual) // Prevent wrapping { gcr_actual = 0; // At this point, power can no longer be cut from the LED drivers, so focus on cutting out extra port if active - if (usb_extra_state != USB_EXTRA_STATE_DISABLED_UNTIL_REPLUG) // If not in a wait for replug state + if (usb_extra_state != USB_EXTRA_STATE_DISABLED_UNTIL_REPLUG) // If not in a wait for replug state { - if (usb_extra_state == USB_EXTRA_STATE_ENABLED) // If extra usb is enabled + if (usb_extra_state == USB_EXTRA_STATE_ENABLED) // If extra usb is enabled { gcr_min_counter++; - if (gcr_min_counter > 200) // 5ms per check = 1s delay + if (gcr_min_counter > 200) // 5ms per check = 1s delay { USB_ExtraSetState(USB_EXTRA_STATE_DISABLED_UNTIL_REPLUG); - usb_extra_manual = 0; // Force disable manual mode of extra port + usb_extra_manual = 0; // Force disable manual mode of extra port if (usb_extra_manual) CDC_print("USB: Disabling extra port until replug and manual mode toggle!\r\n"); else @@ -275,11 +279,11 @@ static void flush(void) { # ifdef USE_MASSDROP_CONFIGURATOR if (!led_enabled) { return; - } // Prevent calculations and I2C traffic if LED drivers are not enabled + } // Prevent calculations and I2C traffic if LED drivers are not enabled # else if (!sr_exp_data.bit.SDB_N) { return; - } // Prevent calculations and I2C traffic if LED drivers are not enabled + } // Prevent calculations and I2C traffic if LED drivers are not enabled # endif // Wait for previous transfer to complete @@ -319,17 +323,19 @@ static void flush(void) { pomod = (uint32_t)pomod % 10000; pomod /= 100.0f; -# endif // USE_MASSDROP_CONFIGURATOR +# endif // USE_MASSDROP_CONFIGURATOR uint8_t drvid; // NOTE: GCR does not need to be timed with LED processing, but there is really no harm if (gcr_actual != gcr_actual_last) { - for (drvid = 0; drvid < ISSI373